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Loren Ashfield

908-410-0856
loren.ashfield@gmail.com
in/lorenashfield

About

Passionate and detail-oriented Computer Engineering student with strong leadership experience and an emphasis on communication. Skilled in hardware and software design with a holistic understanding of computers. Seeking internship opportunities in hardware.

Experience

Hardware Lead

Yonder

08/2024 - Present

  • Leading engineering team responsible for building the hardware/software infrastructure for a high-throughput materials synthesis lab.
  • Running weekly team meetings to track progress, identify blockers, and align on project goals.
  • Developed high-speed mixed-signal PCB for interfacing with custom CMOS materials chip.
  • Spearheaded the design of a next-generation chip optimized for maximum throughput and signal integrity.
  • Wrote robust, containerized lab control API with front-end control software and an ORM layer for database integration.

Project Lead

UCSB Capstone Project

09/2025 - Present

  • Leading a team of 5 students for UCSB Senior Capstone Project partnered with AeroVironment.
  • Designing high-speed carrier board to interface flight controller with cost effective Raspberry Pis for on-board sensors and peripherals.
  • Managing project timeline, tasks, and deliverables with weekly progress reports.

ECE Tutor

University of California, Santa Barbara

02/2025 - 06/2025

  • Tutored students in Digital Design Principles (ECE 152A) and Sensor and Peripheral Interface Design (ECE 153B) for UCSB MESA Program.

Research

Nanoelectronics Research Lab

University of California, Santa Barbara

04/2025 - Present

  • Exploring the possibility of fabricating novel memory using 2D materials.
  • Modeling novel memory structures with DFT simulations using QuantumATK and Sentaurus TCAD.

Microelectronic Design and Application Group

Universidad Carlos III de Madrid

06/2024 - 07/2024

  • Determined susceptibility of consumer embedded processors to radiation induced single-event upsets in space.
  • Wrote low-foortprint benchmarks for ARM Cortex-M and RISC-V microprocessors in C and Assembly, with and without lightweight operating systems like FreeRTOS to simulate real workflows.

Education

University of California, Santa Barbara

M.S. in Electrical and Computer Engineering

Santa Barbara, CA

2025 - 2027

University of California, Santa Barbara

B.S. in Computer Engineering, 3.93 GPA

Santa Barbara, CA

2022 - 2026

Projects

SRAM Design, Built 32kb SRAM array by hand in Cadence Virtuoso, optimized for power and speed.
AI Portrait Generator, Built a fine-tuned Stable Diffusion model via Dreambooth.
Smart Garage Door, Autonomous control using STM32 embedded processor. Manages bluetooth, temperature, and motion detection.
Custom PCs, 7+ years of experience building custom desktop PCs, including full custom water cooling loops and custom operating systems.

Societies and Honors

Dean's Honors, Earned every quarter for having a quarter GPA of 3.75 or higher.
Tau Beta Pi, Member of national engineering honor society, invited for being in top one-eigth of class.
Alpha Tau Omega, Served as social chair, planned, coordinated, and executed large scale trips and events.

Skills

Programming Languages:

Python, C/C++, Assembly, Java, JavaScript/TypeScript, SQL, Rust, Go

Software Tools:

React/Next.js, PostgreSQL, AWS/Cloud, PyTorch, Docker, Git, Linux

Hardware Tools:

Cadence, MMI IC Design Tools, SPICE, KiCad, ModelSim, Quartus, Verilog/VHDL, QuantumATK, TCAD