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Loren Ashfield

908-410-0856
loren@lorenashfield.com
in/lorenashfield

About

Passionate and detail-oriented Electrical Engineering student at UC Santa Barbara. Experienced in mixed-signal IC and PCB design. Skilled in both hardware and software design with a holistic understanding of computers. Seeking work opportunities in hardware design.

Experience

Electrical Engineer

Yonder

08/2024 - Present

  • Designed and managed high-throughput electrochemistry system. Designed mixed-signal ASICs (CMOS microelectrode arrays) in Cadence and low-noise interface PCBs in Altium (also KiCad). Optimized for signal integrity, leakage, and lab reliability.
  • Built end-to-end experimental control stack, from embedded firmware (timing-critical MCU control and device communication) to lab automation APIs and backend services in Python, C, and Rust orchestrating concurrent experiments, robotics, imaging, and instrumentation.
  • Worked part-time while in school; Traveled frequently to Austin and Seattle to work directly with clients and partners.

ECE Tutor

University of California, Santa Barbara

02/2025 - 06/2025

  • Tutored students in Digital Design Principles (ECE 152A) and Sensor and Peripheral Interface Design (ECE 153B) for UCSB MESA Program.

Research

Nanoelectronics Research Lab

University of California, Santa Barbara

04/2025 - Present

  • Exploring the possibility of fabricating novel memory using 2D materials.
  • Modeling novel memory structures with DFT simulations using QuantumATK and Sentaurus TCAD.

Microelectronic Design and Application Group

Universidad Carlos III de Madrid

06/2024 - 07/2024

  • Determined susceptibility of consumer embedded processors to radiation induced single-event upsets in space.
  • Wrote low-footprint benchmarks for ARM Cortex-M and RISC-V microprocessors in C and Assembly, with and without lightweight operating systems like FreeRTOS to simulate real workflows.

Education

University of California, Santa Barbara

M.S. in Electrical and Computer Engineering

Santa Barbara, CA

2025 - 2027

University of California, Santa Barbara

B.S. in Computer Engineering, 3.93 GPA

Santa Barbara, CA

2022 - 2026

Projects

Capstone Project , Leading team of 5 students partnered with AeroVironment. Designed high-speed carrier board in KiCAD to interface proprietary flight controller with Raspberry Pis as a cost effective companion computer.
SRAM Design , Designed 32kb SRAM array in Cadence Virtuoso, optimized for power and speed. Designed routing and layout by hand, verified against DRM/LVS rules.
High-Speed 5Gbps USB-C Splitter , Designed a high-speed 5Gbps USB-C splitter PCB in KiCAD with integrated power delivery.
Smart Garage Door , Autonomous control using STM32 embedded processor. Manages bluetooth, temperature, and motion detection.
Custom PCs , 7+ years of experience building custom desktop PCs, including full custom water cooling loops and custom operating systems.

Societies and Honors

Dean's Honors , Earned every quarter for having a quarter GPA of 3.75 or higher.
Tau Beta Pi , Member of national engineering honor society, invited for being in top one-eighth of class.
Alpha Tau Omega , Served as social chair, planned, coordinated, and executed large scale trips and events.

Skills

Programming Languages:

Python, C/C++, Assembly, Java, JavaScript/TypeScript, SQL, Rust, Go

Software Tools:

React/Next.js/Astro, PostgreSQL, AWS/Cloud, PyTorch, Docker, Git, Linux

Hardware Tools:

Cadence, SPICE, Altium/KiCad, ModelSim, Quartus, Verilog/VHDL, QuantumATK, Sentaurus TCAD