Loren Ashfield logo
Loren Ashfield

About Me

I'm a computer engineer currently pursuing an M.S. in VLSI and Computer Architecture at UC Santa Barbara. My technical background includes computer architecture, CMOS design, PCB design, and low-level software.

In 2024, during my undergraduate studies, I began working part-time at Yonder, a startup developing an autonomous, high-throughput electrochemistry platform for materials discovery. What started as an intern role quickly expanded as the company scaled. Today, while continuing my coursework part-time, I manage Yonder's hardware team, leading the design and deployment of the hardware and software infrastructure behind our experimental systems. My work spans CMOS microelectrode arrays, high-speed mixed-signal PCB design, and the software layers that control experiments and pipeline data into production systems. I also regularly travel on behalf of the company, representing Yonder in meetings with clients and partners, including frequent trips to Austin and Seattle to align development with deployment needs.

Alongside industry work, I've been involved in academic research focused on low-power computing, novel memory technologies, and hardware reliability. This includes modeling next-generation memory structures using DFT and TCAD tools, as well as studying radiation-induced faults in embedded processors for space applications. I also enjoy mentoring and leadership roles, having served as a tutor for upper-division ECE courses at UCSB and currently leading a senior capstone team partnered with AeroVironment.

Outside of classes and work, I'm an avid builder, whether that's custom PCs, embedded systems, or one-off side projects. When I'm not soldering, simulating, or debugging, I enjoy making fresh pasta, hiking the mountains around Santa Barbara, or sitting on my deck overlooking the ocean.